The present invention relates in general to a computer processing subsystems, and in particular to dual port memories and systems and methods of using the same.
A typical computer processing system includes a central processing unit (CPU), and main memory, and other hardware devices, such as storage devices, keyboards, display devices and network controllers. All of these components are generally connected together through at least one bus. In addition, an input/output (input or output or both) subsystem, typically comprised of various I/O subsystem devices distributed throughout the system, is included which controls the interconnections between the computer bus(s), CPU memory and other hardware devices.
Among other things, the I/O subsystem mediates the transfer of data between hardware devices, which may vary in many aspects, such as speed, supply voltage, and bus protocol. Additionally, the I/O subsystem accounts for limitations in the computer processing system standard architecture. Recently, however, the basic I/O subsystem used in the industry has needed modification, in part because advances in the performance of the CPU, memory and other hardware devices have not occurred uniformly. Despite such differences in hardware performance, there remains a desire to maintain various industry standards in the computer processing system architecture. As a result, data transfer rates still vary significantly with any given system.
The I/O subsystem is typically made up of various controller circuits and memory caches or buffers which operate independently as intermediaries between the computer processing system components. Typical I/O subsystem controller circuits may vary in configuration and function according to specific applications, but in general are required to adapt to data structures and to translate between selected hardware protocols to maintain efficient communication within the system. Also, although the I/O subsystem memory cache and buffers may vary in structure and operation according to specific applications, they generally must transfer data at rates that meet or exceed the data transfer rates of the hardware devices connected therewith. The memory cache may also cooperate with an associated controller circuit in adapting the data structure.
The core logic is a particular I/O subsystem device which generally ties the other hardware devices together. Early core logic designs included direct memory access (DMA) controllers, interrupt control devices and a timer-counter device. Later, the industry standard architecture (ISA) bus controller and bus buffer, previously separate I/O subsystem devices, were combined with the core logic chip set. Present core logic designs for a peripheral component interconnect (PCI) bus architecture additionally include the CPU local bus to PCI bridge, a PCI to ISA bridge, to maintain compatibility with earlier ISA bus architectures, and system memory and cache controllers. The implementation of the PCI bus bridges in the core logic is intended to provide a standard architecture for interfacing the CPU with other hardware devices, such as the system memory controller, the cache controller, and the video display adapter or controller. These hardware devices were previously connected directly to the CPU local bus. However, because CPU local busses are different for each CPU, upgrading the CPU required the upgrade of all of the hardware device connections made to CPU local bus. Presently, since these hardware devices connect to the CPU local bus through the core logic of PCI bus, upgrading the CPU nearly requires replacing the CPU chip and the CPU local bus to the PCI bridge chip. However, while providing upgrade capabilities in the system architecture, the present PCI bus and core logic architecture creates a potential bottleneck by channeling all information to and from the CPU through the core logic and the CPU local bus to the PCI bridge chip.
The CPU communicates through the core logic to handle management of the system buses and to execute various offer applications. Currently, most industry computer busses are managed by the CPU. In this capacity, the CPU is a system master and generally provides overall system control in conjunction with the software operating system. The CPU, in addition to managing the data transfers on the busses, still handles execution of the software operating system and software applications. To alleviate the potential bottleneck created by the CPU local bus to PCI bridge, it is desirable to transfer some CPU management functions to the core logic.
In sum, with the advent of high performance processors, memories, and other hardware devices, the differences between the performance capabilities of these hardware devices has increased. The need has, therefore, arisen for improvements to the I/O subsystem and I/O subsystem devices. In particular, a need has arisen for improvements in the core logic to minimize performance conflicts between devices performing independent tasks and operating at different speeds.
In addition, advances in software complexity and the advent of multimedia applications have substantially increased the demand for high speed and large volume data transfers which require channeling large amounts of data between storage devices and display devices or sound devices. Often, the requirements of multimedia applications conflict with the computer processing system architecture which was not designed for such applications. In the past, the CPU handled all data transfers between various computer processing system devices. In order to meet the data transfer demands of multimedia applications, some historical CPU tasks have been delegated to I/O subsystem controllers, but the need still exists for improving the transfer rates of data through the I/O subsystem.
The previously mentioned needs are fulfilled with the present invention. Accordingly, there is provided, in one form, a memory system. The memory system includes a first array of memory cells and a second array of memory cells. The memory system also includes the first column decoder which is connected to the first array of memory cells for selectively accessing a location of cells within the first array of memory cells. A second column decoder is connected to the second array of memory cells for selectively accessing a location of cells within the second array of memory cells. The memory system also includes a transfer circuit for selectively transferring a first data value from a selected location of the first array to the second array and for selectively transferring a second data from a selected location in the second array to the first array.
Additionally, there is provided, in a second form, a memory system. The memory system includes a control circuit for receiving a first plurality of address bits, a first plurality of control bits, a second plurality of address bits, and a second plurality of control bits. The control circuit selectively generates a transfer control signal in response to the first plurality of control bits and the second plurality of control bits. The memory system also includes the first array of memory cells having a first plurality of rows and a first plurality of columns. A first one of the first plurality of rows corresponds to a first predetermined word line in the first one of the first plurality of columns corresponds to a first predetermined bit line. The memory system also includes a second array of memory cells having a second plurality of rows and a second plurality of columns. A first one of the second plurality of rows corresponds to a second predetermined word line and a first one of the second plurality of columns corresponds to a second predetermined bit line. A first column decoder is connected to the first bit line of the first array to selectively access the first array of memory cells. A second column decoder is connected to the second bit line of the second array to selectively access the second array of memory cells. A transfer gate has a first terminal connected to the first predetermined bit line, a second terminal connected to the second predetermined bit line, and a third terminal connected to a source of the transfer control signal. The transfer gate selectively transfers a first data accessed by the first column decoder to the second column decoder and selectively transferring a the second data accessed by the second column decoder to the first column decoder in response to a logic state of the transfer control signal.
Furthermore, there is provided, in a third form, a method for operating a memory system having a first array of memory cells and a second array of memory cells. The first array is associated with a first column decoder and the second array is associated with a second column decoder. The method includes the step of exchanging a first data between the first column decoder and the first array of memory cells. A second data is then exchanged between the second column decoder and the second array of memory cells. A transfer circuit is selectively enabled to transfer the first data value from the first column decoder to the second column decoder. Additionally, the transfer circuit is selectively enabled to transfer the second data value from the second column decoder to the first column decoder.
These and other features, and advantages, will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. It is important to note that the drawings are not intended to represent the only form of the invention.